The present invention relates to shifter circuits, and in particular to level shifter circuits for (in one example) 0.9 volt to 3.3 volt technology with increased switching speed.
The feature size of transistors in CMOS technology continues to shrink as technology advances. As a result, the core supply voltage of the integrated circuit chips also drops. For example, the core supply voltage drops to 0.9V from 1.5V when moving from 0.15=technology to 90 nm technology. However, when the chip is going to interface with outside components, in many cases it needs to be compatible with older technologies with a 3.3V supply. Therefore, a level shifter circuit is required to convert the signals in from the core supply level to the IO supply level in order to communicate with outside components.
The task of converting a 1.5V signal to a 3.3V signal can be fulfilled by a conventional level shifter circuit illustrated in FIG. 1. However, in 90 nm technology or other technologies that provide a very low core supply voltage, the level shifter circuit in FIG. 1 will be insufficient and can only survive with very low speed signals when converting 0.9V signals to 3.3V signals directly.
In a level shifter circuit, as the one in FIG. 1, when the input signal goes from ‘0’ to ‘1’, NMOS transistor N1 changes status from OFF to ON immediately, and NMOS transistor N2 will change status from ON to OFF as the output of inverter 10 changes from ‘1’ to ‘0’. Initially, the output of the level shifter IO_SUPPLY_SIGNAL stays at ‘0’ and net OUT_BAR stays at ‘1’. As a result, pull-up transistor P1 will stay ON and pull-up transistor P2 will stay OFF. However, this is not a balanced status and will be changed as described below.
As we can see now, transistor N1 is trying to drive the net OUT_BAR to low while transistor P1 is trying to keep the net OUT_BAR high. Transistor N1 has to win over transistor P1 to make the switching of status happen. When the net OUT_BAR is driven low enough to turn on transistor P2, the output signal IO_SUPPLY_SIGNAL will rise, without the need of fighting with another transistor since transistor P2 is OFF. When IO_SUPPLY_SIGNAL rises to high enough to turn off transistor P1, the switching process will be accelerated until IO_SUPPLY SIGNAL reaches the IO supply level.
To make sure the level shifter works, the NMOS transistor N1, when driven by a core supply level signal, has to win over PMOS transistor P1 with its source connected to the IO supply and its gate driven by ground under all scenarios. The same rule applies to transistor N2 and transistor P2. As a result, PMOS transistors P1 and P2 have to be made rather weak. Therefore, when in the case of low core supply and high IO supply, the conventional level shifter switches slowly and cannot meet the high-speed signal requirement.
A simulation result is presented in FIG. 4A. It simulates a conventional level shifter trying to handle a 100 MHz 0.9V input signal with an IO supply of 3.6V. 3.6V is a commonly tolerated 3.3V IO supply variation. As can be seen, the switching turn on rise signal 28 is slow.
FIG. 2 illustrates one way to address the problem of slow switching. The level shifter can be done in two steps. First, level shifter 12 converts 0.9V signals to 1.8V signals, after that level shifter 14 converts 1.8V signals to 3.3V signals.
The first stage level shifter of FIG. 2, level shifter 12, is composed of input and output NMOS transistors N10 and N20, respectively, corresponding to transistors N1 and N2 of FIG. 1. PMOS transistors P10 and P20 correspond to transistors P1 and P2 of FIG. 1. However, an intermediate supply of 1.8V is used, instead of the 3.3V supply of FIG. 1. Level shifter 12 uses an inverter 16 similar to inverter 10 of FIG. 1. An intermediate voltage level 20 is provided to a second stage level shifter circuit 14.
The second stage level shifter circuit 14 consists of NMOS transistors N12 and N22, joined by inverter 18. Pull-up PMOS transistors P12 and P22 are provided. Here, the supply is 3.3V, with the input being in the 1.8V range.
The drawbacks of the two level scheme of FIG. 2 are:
1. An additional power supply such as 1.8V needs to be generated;
2. Additional oxide masks are needed to provide 1.8V transistors; and
3. Two-steps conversion increases propagation delay of the signals.